VP AI System Solutions, Applied Materials
Heterogeneous Integration in the AI Era
Wednesday, January 25, 2023 10:10-10:40
About the Speaker: Subi Kengeri is the Vice President of AI Systems Solutions at Applied Materials. His team is chartered with the goal of architecting next generation AI Systems leveraging Applied’s fundamental innovations.
Prior to joining Applied, Subi was the CTO and vice president of world-wide client solutions at Globalfoundries, responsible for enabling differentiated SoC and systems solutions. Subi joined Globalfoundries in 2009 as the vice president of global design solutions responsible for world-wide design engineering and semiconductor ecosystem development. He was responsible for determining technology feasibility, competitiveness, and manufacturability of technology platform through cross-functional collaboration of customers, R&D and ecosystem. In the role of vice president of CMOS Platforms Business Unit, Subi was responsible for business results.
Subi started his SoC design engineering career at Texas Instruments in 1991 and prior to joining Globalfoundries, he was the senior director of design-technology platform and head of North America Design center, at TSMC. Subi has been granted 47 U.S. design engineering patents and has given over 100 invited talks and press interviews.
Abstract: Semiconductor industry is at an inflection point. AI Compute requirements, specifically TOPs/W/$ needs, are growing exponentially while facing Moore’s Law scaling constraints. The future of the semiconductor industry is going to increasingly rely on new materials and newer approaches to integrating system functions. There will be a growing need to take a complete system to technology co-optimization approach with specific focus on system architecture, advanced packaging and software. This talk will cover why and how Heterogeneous Integration enables and catalyzes solutions required to meet system design challenges in the AI era.
About Applied Materials:
Leverage Agents to Boost Chiplet Design and Reliability
Wednesday, January 25, 2023 10:50-11:20
About the Speaker: Nitza Basoco is VP Business Development at proteanTecs, the leading provider of deep data analytics for advanced electronics monitoring. She focuses there on partnership strategies and ecosystem growth. She has a broad background in management, test development, product engineering, supply chain, and operations. Before joining proteanTecs, she was VP Operations at Synaptics and held engineering leadership positions at MaxLinear and test engineering positions at Broadcom and Teradyne. She has developed test packages for video processors and pioneered stack die testability. She earned a Master of Engineering degree from MIT. She has also been an active volunteer with the GSA Women’s Leadership Initiative.
Abstract: There are several challenges the industry has yet to overcome to reach a mature, commercially viable market for chiplets. Designers must worry about effects such as chiplet-package interaction and chiplet-chiplet interaction. They must also worry about thermal, power, and signal integrity issues at both the chiplet and the package level together with multiple die-to-die interfaces.
How can manufacturers guarantee quality and yield of packaged systems, while overcoming the existing test blind spots? How can service providers assure reliability and lifetime functionality of these systems in the field, without in-mission visibility?
Wouldn’t you love to have an army of agents (like MI6 or the CIA) that would lurk everywhere, sending you back regular reports on what’s going on? You’d have all the information you need to track down bugs, perform optimizations, and look for lurking problem areas. Early detection equals significant cost savings.
Of course, like MI6 or the CIA, you next must determine what all that information means. The data deluge, as they say. In the chip world, you need cloud and edge analysis with a variety of tools to dice and slice the data and decide what to do.
Well, you can have all that today. It’s called agent-based monitoring in which you place agents in the systems, and they report back to you. Results on chiplet-based systems show you can perform system optimization from design all the way to packaging, assembly, and test. The applications enable per-lane grading, defect detection, spare lane swapping, and time to failure prediction. With advanced telemetry-based analytics, even heterogeneous integration becomes predictable, reliable, cheaper, and faster.
proteanTecs is the leading provider of deep data analytics for advanced electronics monitoring. Trusted by global leaders in the datacenter, automotive, communications and mobile markets, the company provides system health and performance monitoring, from production to the field. By applying machine learning to novel data created by on-chip monitors, the company’s deep data analytics solutions deliver unparalleled visibility and actionable insights—leading to new levels of quality and reliability. Founded in 2017 and backed by world-leading investors, the company is headquartered in Israel and has offices in the United States, India and Taiwan. For more information, visit www.proteanTecs.com.
Vice President of Business Development, proteanTecs
The CHIPS Act: How we got here and why we need to build a robust chiplet ecosystem
Wednesday, January 25, 2023 11:30-Noon
About the Speaker: Daniel Armbrust is co-founder and director of Silicon Catalyst which incubates semiconductor startups. Its portfolio companies have raised more than $400k in venture funding and are valued at over $1.5B. Armbrust serves as an advisor, board member, board chairman and angel investor for many semiconductor startups. Daniel is an affiliate with Lawrence Berkeley National Labs and recently was appointed to the Industrial Advisory Committee, which advises the Department of Commerce on the R&D strategy for the CHIPS Act. He served as President and CEO of the SEMATECH semiconductor consortium and held various positions in semiconductor manufacturing and development over 25 years at IBM.
Daniel’s remarks today are made in his personal capacity, and his remarks should not be attributed to the Department of Commerce, the Industrial Advisory Committee of the CHIPS Act, or the US Government.
Abstract: The semiconductor industry has evolved over six decades from its origin in startups, venture capital, and vertically integrated companies to a robustly growing, horizontally integrated and concentrated supply chain. Chiplets are one of the major trends that will shape the future winners and losers and resulting industry structure. Chiplets will also be essential for accelerating startup innovation and addressing designer productivity.
While die aggregation has become a reality for many important companies, replicating that success has yet to be achieved for packaging aggregation of commonly available chiplets. Several critical business model challenges and ecosystem developments are required to get to a vibrant standards- based chiplets world.
With the passage of the $52B CHIPS Act in the U.S. and similar initiatives elsewhere in the world, there should be ample opportunities to accelerate the timelines and benefits for industry, government and academic stakeholders.
About Silicon Catalyst: Silicon Catalyst actively works with over 300 investors, from large VCs to smaller firms, multiple angel groups, tier-one corporate VCs and individual angels
Open Architectures to Accelerate
Thursday, January 26, 2023 10:10-10:40
About the Speaker: Bob Brennan is Vice President of Customer Solutions Engineering for Intel Foundry Services. He leads “System of Chips”, Architecture, UCIe, and multi-ISA (x86, ARM, RISC-V) portions of the “System Foundry.” Bob is also a board member for RISC-V International. Previously, he served as Vice President of Emerging Memory & Systems at Micron, and as Senior Vice President of the Memory Solutions Lab at Samsung. During his previous tenure at Intel, Bob held senior technical positions in architectures and design. He earned an MSEE at the University of Virginia. Widely recognized as a leading processor architect, Bob is frequently interviewed in the trade and technical press and has been a featured speaker at many events, including Design Automation Conference.
Abstract: There is an exponential growth in demand for workload specific compute in artificial intelligence (both training and inference), network and storage acceleration, 5G/6G edge servers, media acceleration, high performance compute (ex. Vector processing), graphics, and gaming. The industry is facing many architectural challenges to improve cost, performance, power, security, etc. to meet this demand. The solution will require a broad alignment around standardized open architectures from the ISA to the SoC level, alignment of the IP supplier ecosystem, cooperation in standards, new EDA tools, and support from foundries and packaging suppliers.
As Dennard’s scaling and Moore’s law diminish, these open architectures must embrace disaggregation. The new disaggregated architectures will need new packaging technologies to be co-optimized with interconnect technologies with full support from Foundries and the IP Ecosystem. New EDA tools will be needed to optimize the overall silicon partitioning and accelerate the development cycles of each partition.
This talk will highlight some of the recent progress in the industry, and a call to collaborate on enabling and supporting these new architectures.
About Intel Foundry Services Customer Engineering: IFS was established in 2021 to help meet the surging global demand for advanced semiconductor manufacturing capacity. IFS is differentiated from other foundry offerings with a combination of leading-edge process and packaging technology, a world-class IP portfolio, and committed capacity in the United States and Europe. IFS customers will reap the benefits of Intel’s recently announced factory expansions at existing sites, as well as plans for major new investments in greenfield sites in Ohio and Germany.
Intel Foundry Services Customer Engineering
Speeding up Chiplet-Based Design Through Hardware Emulation
Thursday, January 26, 2023 10:50-11:20
About the Speaker:Jim Finnegan is COO at Corigine, a maker of network processors and SmartNICs. Before joining Corigine, he worked at Intel, where he was general manager of both the Network Processor Division and the Communication Infrastructure Group’s Technology Office. He has over 30 years’ experience in the networks and communications businesses, including positions at Digital Equipment and Tellabs. He earned Bachelor’s and Master’s degrees in electronic engineering from Queen’s University Belfast (Northern Ireland).
Abstract: Chiplets are here to stay, as shown by all the large semiconductor companies adopting them. However, we clearly need new tools to cope with more complexity, new stages, and huge amounts of data. One powerful solution is a combined prototyping/ emulation/development system based on large FPGAs. It can provide not only faster-than-software turnaround time, but also features for collecting and analyzing data, introducing design-for-test and design-for-manufacturing features, allowing software verification before tapeout, and ensuring a high level of security. Future versions could validate 3rd party IP and designs to allow an open ecosystem and promote design reuse. The long-term result can be easy access to “best-in-class” chiplets and reduced time-to-market.
About Corigine: Corigine is a fabless semiconductor company that designs and delivers leading edge I/O and networking products, IPs, and EDA tools.
Founded in 2015, the company has R&D centers and sales offices worldwide including Santa Clara, Shanghai, Nanjing, Beijing, London, Centurion and Cape Town etc. The company is led by a team of renowned silicon professionals that have pioneered generations of innovations in the semiconductor industry.
Chiplets are here to stay, as shown by all the large semiconductor companies adopting them. However, we clearly need new tools to cope with more complexity, new stages, and huge amounts of data. One powerful solution is a combined prototyping / emulation / development system based on large FPGAs. It can provide not only faster-than-software turnaround time, but also features for collecting and analyzing data, introducing design-for-test and design-for-manufacturing features, allowing software verification before tapeout, and ensuring a high level of security. Future versions could validate 3rd party IP and designs to allow an open ecosystem and promote design reuse. The long-term result can be easy access to “best-in-class” chiplets and reduced time-to-market.
Ph.D. Vice President Market Intelligence & Innovation
Open Compute Project Foundation
Head Open Domain-Specific Architecture (ODSA) project
Open Compute Project Foundation
Speeding up Chiplet-Based Design Through Hardware Emulation
Thursday, January 26, 2023 11:30-Noon
About the Speakers:
Cliff Grossner is Vice President Market Intelligence & Innovation at the Open Compute Project Foundation, where he leads market intelligence and drives awareness of OCP, establishes training and certification programs, and guides inventors in presenting early-stage company ideas to investors. Cliff is also active in OCP’s Future Technologies Initiative. Before joining OCP, he headed the Cloud and Data Research Practice at Omdia, where he focused on overall research quality and worked on programs in cloud services, data center compute and networking, and data center infrastructure. He previously held senior positions at Alcatel-Lucent, Bell Labs, and Nortel. He earned his PhD at McGill University (Canada) and holds over 10 patents in networking and telecommunications.
Bapi Vinnakota currently leads the Open Domain-Specific Architecture (ODSA) sub-project within the Open Compute Project (OCP). At OCP, he is working on the open chiplet economy, including the Bunch of Wires (BoW) die-to-die interconnect standard. He previously held engineering management positions at Broadcom, Netronome, and Intel. He has long been a leader in open communities, including creating Open-NFP, which enables programmable data plane acceleration research. He has several publications on ODSA and BoW, including an invited talk at the ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP), presentations at Hot Interconnects, and an article in IEEE Micro. He has also been a professor at the University of Minnesota. He earned a PhD in computer engineering from Princeton University.
Abstract: Chiplets have arrived as the way to design very large chips at leading-edge nodes. But how can we take full advantage of the drop-in approach they offer, allowing designers to easily include existing designs at older nodes, IP, and chiplets from outside sources? The OCP believes that an open chiplet economy is the way to go. It will serve the needs of chiplet creators, ASIC designers, and those providing support such as design tools, test facilities, and professional services. Such an economy requires standards, tools, and best practices. The OCP is already pursuing projects that standardize design models, help establish 3rd party testing, improve supply chain methods, define best practices for assembly, and create a standard high- performance, low-power die-to-die interface. The open chiplet economy will benefit large and small organizations alike, and will create huge opportunities for economic growth worldwide.
About Open Compute Project:
Special Presentation #1
Wednesday, January 25, 2023 10:40-10:50
Enabling an Open Chiplet Ecosystem at the Package Level
About the Speaker:
Abstract: The UCIe Consortium is an industry consortium dedicated to advancing UCIe™ (Universal Chiplet Interconnect Express™) technology, an open industry standard that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. UCIe Consortium is led by key industry leaders Advanced Semiconductor Engineering, Inc. (ASE), Alibaba, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, NVIDIA, Qualcomm Incorporated, Samsung Electronics, and Taiwan Semiconductor Manufacturing Company.
About UCIe™ Consortium: UCIe™ (Universal Chiplet Interconnect Express™) is an open specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.
AMD, Arm, Advanced Semiconductor Engineering, Inc. (ASE), Google Cloud, Intel Corporation, Meta, Microsoft, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing Company are dedicated to this open industry standard organization to promote and further develop the technology, and to establish a global ecosystem supporting chiplet design.
Marketing WorkGroup Chair, UCIe™ Consortium
Board Member, RISC-V / CEO
Ventana Micro Systems
Special Presentation #2
RISC-V and Chiplets Powering the Next Leap Forward in Compute Systems Architecture
Wednesday, January 25, 2023 11:20-11:30
About the Speaker: Balaji Baktha is the founder and CEO of Ventana Micro Systems, a leader in high-performance RISC-V processors. He is an experienced semiconductor executive and a serial technology entrepreneur and investor with a proven track record in founding and exiting several successful startups over more than 30 years in Silicon Valley. Balaji is a board member of RISC-V International as well as several other startups, and a Limited Partner and Senior Advisor at PE and VC funds.
Prior to Ventana, Balaji was the founder and CEO of Veloce Technologies, the world’s first 64-bit ARM based high performance processor for cloud-compute (acquired by AppliedMicro). Before Veloce, Balaji was the VP and GM of the Communications Business at Marvell Semiconductor where he managed multiple product groups including compute, wired and wireless networking, and Enterprise Storage SoCs. Before Marvell, Balaji co-founded Platys, a startup that pioneered iSCSI storage networking and was subsequently acquired by Adaptec (now Microsemi). Prior to Platys, Balaji founded Shuttle Technologies (acquired by SCM Micro) to build the first digital media & storage I/O SoCs for Apple, Sony, and HP.
About RISC V: RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community. More than 3,180 RISC-V members across 70 countries contribute and collaborate to define RISC-V open specifications as well as convene and govern related technical, industry, domain, and special interest groups. RISC-V combines a modular technical approach with an open, royalty-free license model — meaning that anyone, anywhere can benefit from the IP contributed and produced by RISC-V. RISC-V enables the community to share technical investment, contribute to the strategic future, create more rapidly, enjoy unprecedented design freedom, and substantially reduce the cost of innovation.
Special Presentation #3
Thursday, January 26, 2023 10:40-10:50
Supporting the Chiplet Integration Ecosytem
The heterogeneous integration ecosystem has been growing steadily over the past 15 years as advanced wafer-level packaging, silicon interposer, and 3D stacking technologies have grown from concept to reality. More recently, chiplet integration technologies became part of the conversation, requiring collaboration across the supply chain.
About the Speaker: Dean W. Freeman: is the technology advisor for 3DIncites and Kiterocket, and a contributor to 3D InCites where he covers heterogeneous integration and sustainability issues as they pertain to the greater semiconductor industry. Mr. Freeman has over 40 years of life experience in the semiconductor manufacturing and materials space, where he has had experience in nearly every sector of the semiconductor manufacturing process. Mr. Freeman has worked both in the fab, and for semiconductor equipment manufacturing companies. Prior to joining 3DIncites, Mr. Freeman was a research VP for Gartner tracking semiconductor manufacturing, process technology, and multiple aspects of the internet of things. Mr. Freeman has also worked at FSI, Watkins Johnson, Lam Research, and Texas Instruments. Mr. Freeman has 9 process and equipment patents as well as multiple articles in various trade and technical journals. Mr. Freeman has a BS in Chemistry and Earth Science from Whitworth College and a MS in Physical Chemistry from the University of Nevada Reno.
Abstract: The heterogeneous integration ecosystem has been growing steadily over the past 15 years as advanced wafer-level packaging, silicon interposer, and 3D stacking technologies have grown from concept to reality. More recently, chiplet integration technologies became part of the conversation, requiring collaboration across the supply chain.
The 3DinCites community was established in 2009 to provide a forum for discussion across the heterogeneous integration supply chain. It is a place to find answers, voice opinions and recognize the successes of companies through its annual 3D InCites Awards program. The speaker will touch on the history of the 3D InCites community, its recent role in supporting the Chiplet Ecosystem, and how attendees can participate in the future.
The 3D inCites community was established in 2009 to provide a forum for discussion across the heterogeneous integration supply chain. It is a place to find answers, voice opinions and recognize the successes of companies through its annual 3D InCites Awards program. The speaker will touch on the history of the 3D InCites community, its recent role in supporting the Chiplet Ecosystem, and how attendees can participate in the future.
Co-Chair, SNIA Technical Council
Special Presentation #4
Thursday, January 26, 2023 11:20-11:30
New Storage Technologies and Trends: Accelerating through Standards and Open Communities
With rapidly changing technologies and an increasing variety of options, managing both data and storage systems is an increasingly complex proposition. Mark will look at some of the key recent and emerging storage technologies, and talk about how standards, industry consortiums, and open communities are working together to accelerate adoption of these new technologies by partnering together
About the Speaker:
Mark A. Carlson, Principal Engineer, Industry Standards at Toshiba, has more than 35 years of experience with Networking and Storage development and more than 18 years experience with Java technology. Mark was one of the authors of the CDMI Cloud Storage standard. He has spoken at numerous industry forums and events. He is the co-chair of the SNIA Cloud Storage and Object Drive technical working groups, and serves as chair on the SNIA Technical Council.
About SNIA: The Storage Networking Industry Association is a not-for-profit global organization, made up of member companies spanning the storage market. As a recognized and trusted authority for storage leadership, standards, and technology expertise worldwide, SNIA’s mission is to lead the storage industry in developing and promoting vendor-neutral architectures, standards, and educational services that facilitate the efficient management, movement, and security of information